1. Field of the Invention
The present invention relates to a static semiconductor memory device capable of detecting a failure in a standby mode.
2. Description of the Background Art
Referring to FIG. 23, a static memory cell (SRAM (Static Random Access Memory)) 10 has p-channel MOS transistors 1 and 2, n-channel MOS transistors 3 to 6, and storage nodes N1 and N2. The p-channel MOS transistor 1 is connected between a power source node 35 and the storage node N1, and the p-channel MOS transistor 2 is connected between the power source node 35 and the storage node N2. The n-channel MOS transistor 3 is connected between the storage node N1 and a ground node 36, and the n-channel MOS transistor 4 is connected between the storage node N2 and the ground node 36. A voltage on the storage node N1 is applied to the gate terminals of the p-channel MOS transistor 2 and the n-channel MOS transistor 4, and a voltage on the storage node N2 is applied to the gate terminals of the p-channel MOS transistor 1 and the n-channel MOS transistor 3. The n-channel MOS transistor 5 is connected between the storage node N1 and a bit line BL, and the n-channel MOS transistor 6 is connected between the storage node N2 and a bit line /BL. The n-channel MOS transistors 5 and 6 are turned on/off by a word line (WL).
When the potential on the storage node N1 is at the H (logical high) level and that on the storage node N2 is at the L (logical low) level, the memory cell 10 stores data xe2x80x9c1xe2x80x9d. When the potential on the storage node N1 is at the L level and that on the storage node N2 is at the H level, the memory cell 10 stores data xe2x80x9c0xe2x80x9d.
When the data xe2x80x9c1xe2x80x9d is written in the memory cell 10, the potential on the bit line BL is held H level and the potential on the bit line /BL is held L level. When the word line (WL) is activated, the n-channel MOS transistors 5 and 6 are turned on, the potential on the storage node N1 goes H level which is the same as the potential on the bit line BL, and the potential on the storage node N2 goes L level which is the same as the potential on the bit line /BL. Accordingly, the p-channel MOS transistor 1 is turned on and the n-channel MOS transistor 3 is turned off, so that the potential on the storage node N1 is latched at the H level. The p-channel MOS transistor 2 is turned off and the n-channel MOS transistor 4 is turned off, so that the potential on the storage node N2 is latched at the L level. After that, when the word line (WL) is inactivated, the n-channel MOS transistors 5 and 6 are turned off, the potential on the storage node N1 is held H level, the potential on the storage node N2 is held L level, and the data xe2x80x9c1xe2x80x9d is written in the memory cell 10. When the data xe2x80x9c0xe2x80x9d is written in the memory cell 10, the potential on the bit line BL is held L level and the potential on the bit line /BL is held H level. The same writing operation as that in the case where the data xe2x80x9c1xe2x80x9d is written is performed.
In the case of reading the data xe2x80x9c1xe2x80x9d from the memory cell 10, by making the word line (WL) active, the n-channel MOS transistors 5 and 6 are turned on to make the memory cell 10 active. Since the potential on the storage node N1 is H level, the p-channel MOS transistor 2 is turned off, the n-channel MOS transistor 4 is turned on, a current flows from the bit line /BL to the ground node 36 via the n-channel MOS transistors 4 and 6, and the potential on the bit line /BL goes L level. The p-channel MOS transistor 1 is turned on and the n-channel MOS transistor 3 is turned off, so that the current flows from the power source node 35 to the bit line BL via the p-channel MOS transistor 1 and the n-channel MOS transistor 5, and the potential on the bit line BL goes H level.
The operation in the case of reading the data xe2x80x9c0xe2x80x9d from the memory cell 10 is the same as that in the case of reading the data xe2x80x9c1xe2x80x9d.
As obviously understood from FIG. 23, the memory cell 10 is what is called a full CMOS (Complementary MOS) type SRAM constructed by six MOS transistors. Since a memory cell of this type is constructed only by MOS transistors, a path through which a direct current flows does not exist in a state where data is held. Only a very slight amount of current (the order of 10xe2x88x9215A) such as a sub-threshold current or junction leak current flows. In a memory cell of this type, therefore, a standby current of about 0.1 xcexcA can be realized.
An operation test is conducted on the memory cell 10 before shipment. The operation test includes a test of writing/reading data to/from the memory cell 10 and a retention test. The writing/reading test is a test for determining whether the memory cell is good or not by writing predetermined data to the memory cell 10, reading the written data, and checking whether the read data coincides with the written data or not. The retention test is conducted after the writing/reading test, by holding a voltage to be applied to the memory cell 10 so as to be lower than an external source voltage in normal operation, after elapse of a predetermined time, reading the data from the memory cell 10, and checking whether the written data is retained or not, thereby determining whether the memory cell is good or not.
FIG. 24 shows the profile of a voltage applied to the memory cell 10 at the time of an operation test. During a period T1, 3.3V as an external power source voltage is applied to the memory cell 10 and the writing/reading test is carried out. During a period T2, a voltage applied to the memory cell 10 is lowered from 3.3V to a range from 1.0 to 1.5V and held. After that, during a period T3, 3.3V as the external source voltage is applied to the memory cell 10 and data is read.
When a foreign matter is adhered to the memory cell 10, however, as shown in FIG. 23, a leak current 91 flows between the power source node 35 and the storage node N2. When the storage node N1 is held H level and the storage node N2 is held L level, the p-channel MOS transistor 2 is turned off and the n-channel MOS transistor 4 is turned on. Consequently, an ON-state current 92 flows from the storage node N2 via the n-channel MOS transistor 4 to the ground node 36. In this case, even if the leak current 91 of a few xcexcA flows due to a foreign matter, under normal operation conditions of applying an external source voltage of about 3.3V to memory cells, the ON-state current is 10 xcexcA or larger, and the SRAM operates normally. However, a current in the standby mode is abnormal. In order to detect a memory cell having an abnormal current in a standby mode by an operation test, it is necessary to decrease the ON-state current of the n-channel MOS transistor 4 shown in FIG. 23 to 1 xcexcA or lower. In order to set the ON-state current of the n-channel MOS transistor 4 to 1 xcexcA or lower, a voltage applied to the power source node 35 of the memory cell 10 has to be set to about a threshold voltage Vth of the n-channel MOS transistor 4 at the time of the retention test.
It is, however, difficult to apply the voltage which is about the threshold voltage Vth from the outside to the memory cell due to an influence of temperature fluctuation or the like, and there is a problem such that a memory cell having an abnormal current in a standby mode due to a leak current cannot be detected.
An object of the invention is, therefore, to provide a static semiconductor memory device capable of detecting a memory cell having an abnormal current in a standby mode by an operation test.
A static semiconductor memory device according to the invention has: a plurality of static memory cells provided between a first node and a second node; a control terminal for receiving a control signal; a test mode signal generating circuit generating an activated test mode signal when a voltage level of the control signal is equal to or higher than a predetermined level and generating an inactivated test mode signal when the voltage level is lower than the predetermined level; and a voltage setting circuit setting a voltage between the first and second nodes as a test voltage in response to the activated test mode signal and setting a voltage between the first and second nodes as an external source voltage in response to the inactivated test mode signal. The test voltage lies in a range from 0V to a threshold voltage of a MOS transistor as a component of the memory cell.
In the static semiconductor memory device according to the invention, the external source voltage is applied across a memory cell in a normal operation mode, and a voltage in a range from 0V to the threshold voltage of the MOS transistor is applied across a memory cell in a test mode. According to the invention, therefore, a memory cell having an abnormal current in a standby mode can be detected by a data retaining test. According to the invention, the time of an operation test on the static semiconductor memory device can be shortened.
Preferably, the voltage setting circuit in the static semiconductor memory device includes: a voltage supply circuit supplying the threshold voltage to the first node in response to the activated test mode signal and supplying the external source voltage to the first node in response to the inactivated test mode signal; and a ground voltage supplying terminal supplying a ground voltage to the second node.
The voltage setting circuit supplies the threshold voltage or the external source voltage to the first node by the voltage supply circuit and supplies a ground voltage to the second node by the ground voltage supplying terminal, thereby setting the voltage across a memory cell as the external source voltage in a normal operation and setting the voltage across a memory cell as the threshold voltage in a test mode. By switching the voltage to be supplied to the cell Vcc line of the memory cell, a test capable of detecting a memory cell having an abnormal current in a standby mode can be conducted. A memory cell having an abnormal current in a standby mode can be detected in a short time.
Preferably, a MOS transistor as a component of the voltage supply circuit has the same shape and placement as those of a MOS transistor included in a memory cell.
By changing only an interconnection without changing the placement of the MOS transistor as a component of the memory cell, the voltage supply circuit is fabricated. According to the invention, therefore, the memory cells and the voltage supply circuit can be simultaneously fabricated by a process of fabricating the memory cells.
Preferably, the voltage supply circuit in the static semiconductor memory device is constructed by using a MOS transistor included in one of the plurality of memory cells.
By changing the interconnection of the MOS transistor as a component of one of the plurality of memory cells included in the static semiconductor memory device, the voltage supply circuit is fabricated. According to the invention, therefore, the voltage supply circuit for applying a voltage in a range from 0V to the threshold voltage across a memory cell in a test mode can be provided within the static semiconductor without increasing the area.
Preferably, the voltage supply circuit includes: a first MOS transistor of a first conduction type provided between an external power source node and the first node; second and third MOS transistors of a second conduction type connected in series between the first node and a ground node; and a resistive element connected in parallel with the first MOS transistor between the external source node and the first node. The first MOS transistor is turned off in response to the activated test mode signal and is turned on in response to the inactivated test mode signal, the second MOS transistor is connected as a diode between the first node and the third MOS transistor, and the third MOS transistor is turned on in response to the activated test mode signal and is turned off in response to the inactivated test mode signal.
The second MOS transistor supplies the threshold voltage to the first node in response to the activated test mode signal and the first MOS transistor supplies the external source voltage to the first node in response to the inactivated test mode. According to the invention, therefore, the voltage supply circuit can be fabricated by using a MOS transistor as a component of a memory cell. As a result, the threshold voltage can be stably supplied to the first node of the memory cell.
Preferably, the resistive element is either a resistor or a MOS transistor of a first conduction type of which resistance value in an ON state is larger than a resistance value in an ON state of the MOS transistor as a component of the memory cell.
A MOS transistor of the first conduction type or a resistor is fabricated as a resistive element in the same process as the process for fabricating memory cells, thereby forming the voltage supply circuit. According to the invention, therefore, when the MOS transistor of the first conduction type is used as a resistive element, the voltage supply circuit can be constructed only by MOS transistors. When the resistor is used as a resistive element, it is sufficient to form the resistor on the layers of the MOS transistors, so that the area occupied by the voltage supply circuit can be reduced.
Preferably, the voltage setting circuit in the static semiconductor memory device includes: a voltage supply circuit supplying a ground voltage to the first node in response to the activated test mode signal and supplying the external source voltage to the first node in response to the inactivated test mode signal, and a ground voltage supplying terminal supplying the ground voltage to the second node.
The voltage setting circuit supplies the ground voltage or the external source voltage to the first node by the voltage supply circuit and supplies the ground voltage to the second node of a memory cell by the ground voltage supplying terminal, thereby setting the voltage across the memory cell as the external source voltage in a normal operation node and setting the voltage across the memory cell as 0V in a test mode. By switching the voltage to be supplied to the cell Vcc line of a memory cell, therefore, a test capable of detecting a memory cell having an abnormal current in a standby mode can be conducted. A memory cell having an abnormal current in a standby mode can be detected in a short time.
Preferably, the voltage supply circuit in the static semiconductor memory device includes: a first MOS transistor of a first conduction type provided between an external source node and the first node; and a second MOS transistor of a second conduction type connected between the first node and a ground node. The first MOS transistor is turned off in response to the activated test mode signal and is turned on in response to the inactivated test mode signal, and the second MOS transistor is turned on in response to the activated test mode signal and is turned off in response to the inactivated test mode signal.
The second MOS transistor supplies the ground voltage to the first node in response to the activated test mode signal, and the first MOS transistor supplies the external source voltage to the first node in response to the inactivated test mode signal. According to the invention, therefore, the voltage supply circuit can be fabricated by using the MOS transistor as a component of a memory cell. As a result, the threshold voltage can be stably supplied to the first node of a memory cell in a test mode.
Preferably, the voltage setting circuit in the static semiconductor memory device includes: a source voltage supplying terminal supplying the external source voltage to the first node; and a voltage supply circuit supplying a voltage obtained by subtracting the threshold voltage from the external source voltage to the second node in response to the activated test mode signal and supplying a ground voltage to the second node in response to the inactivated test mode signal.
The voltage setting circuit supplies the external source voltage to the first node of a memory cell by the source voltage supplying terminal and supplies the ground voltage or a voltage obtained by subtracting the threshold voltage from the external source voltage to the second node by the voltage supply circuit, thereby setting the voltage across the memory cell as the external source voltage in a normal operation mode and setting the voltage across the memory cell as the threshold voltage in a test mode. By switching the voltage to be supplied to the cell GND line of a memory cell, therefore, a test capable of detecting a memory cell having an abnormal current in a standby mode can be conducted. A memory cell having an abnormal current in a standby mode can be detected in a short time.
Preferably, a MOS transistor as a component of the voltage supply circuit in the static semiconductor memory device has the same shape and placement as those of a MOS transistor included in a memory cell.
The voltage supply circuit is fabricated by changing only the interconnection without changing the placement of the MOS transistor as a component of a memory cell. According to the invention, therefore, the memory cells and the voltage supply circuit can be simultaneously fabricated by the process of fabricating the memory cells.
Preferably, the voltage supply circuit in the static semiconductor memory device is constructed by using a MOS transistor included in one of the plurality of memory cells.
By changing the interconnection of the MOS transistor as a component of one of the plurality of memory cells included in the static semiconductor memory device, the voltage supply circuit is fabricated. According to the invention, therefore, the voltage supply circuit for applying a voltage in a range from 0V to the threshold voltage across a memory cell in a test mode can be provided in the static semiconductor memory device without increasing the area.
Preferably, the voltage supply circuit in the static semiconductor memory device includes: first and second MOS transistors of a first conduction type provided in series between an external power source node and the second node; a third MOS transistor of a second conduction type provided between the second node and a ground node; and a resistive element connected in parallel with the third MOS transistor between the second node and the ground node. The first MOS transistor is turned on in response to the activated test mode signal and is turned off in response to the inactivated test mode signal, the second MOS transistor is connected as a diode between the first MOS transistor and the first node, and the third MOS transistor is turned off in response to the activated test mode signal and is turned on in response to the inactivated test mode signal.
In response to the activated test mode signal, the second MOS transistor supplies a voltage obtained by subtracting the threshold voltage from the external source voltage to the second node. In response to the inactivated test mode signal, the third MOS transistor supplies the ground voltage to the second node. According to the invention, therefore, the voltage supply circuit can be fabricated by using the MOS transistor as a component of a memory cell. As a result, the voltage obtained by subtracting the threshold voltage from the external source voltage can be stably supplied to the second node of a memory cell in a test mode.
Preferably, the resistive element in the voltage supply circuit is either a resistor or a MOS transistor of a second conduction type of which resistance value in an ON state is larger than a resistance value in an ON state of the MOS transistor as a component of the memory cell.
In the process of fabricating memory cells, the MOS transistor of the second conduction type or the resistor is fabricated as a resistive element, thereby forming the voltage supply circuit. According to the invention, therefore, when the MOS transistor of the second conduction type is used as a resistive element, the voltage supply circuit can be constructed only by MOS transistors. When the resistor is used as a resistive element, it is sufficient to form the MOS transistor on the layer of the MOS transistors, so that the area occupied by the voltage supply circuit can be reduced.
Preferably, the voltage setting circuit in the static semiconductor memory device includes: a source voltage supplying terminal supplying the external source voltage to the first node; and a voltage supply circuit supplying the external source voltage to the second node in response to the activated test mode signal and supplying a ground voltage to the second node in response to the inactivated test mode signal.
The voltage setting circuit supplies the external source voltage to the first node in a memory cell by the source voltage supply terminal and supplies the ground voltage or the external source voltage to the second node by the voltage supply circuit, thereby setting the voltage across the memory cell as the external source voltage in a normal operation and setting the voltage across the memory cell as 0V in a test mode. By switching the voltage to be supplied to the cell GND line in the memory cell, therefore, a test capable of detecting a memory cell having an abnormal current in a standby state can be conducted. A memory cell having an abnormal current in a standby mode can be detected in a short time.
Preferably, the voltage supply circuit in the static semiconductor memory device includes: a first MOS transistor of a first conduction type provided between an external source node and the second node; and a second MOS transistor of a second conduction type connected between the second node and a ground node. The first MOS transistor is turned on in response to the activated test mode signal and is turned off in response to the inactivated test mode signal, and the second MOS transistor is turned off in response to the activated test mode signal and is turned on in response to the inactivated test mode signal.
In response to the activated test mode signal, the first MOS transistor supplies the external source voltage to the second node in a memory cell. In response to the inactivated test mode signal, the second MOS transistor supplies the ground voltage to the second node. According to the invention, therefore, the voltage supply circuit can be fabricated by using a MOS transistor as a component of a memory cell. As a result, the external source voltage can be stably supplied to the second node in a memory cell in a test mode.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.